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Verilog Hardware Description Language, Mixed Signals and Sensors

Greetings!
The Institute of Computer Engineers of the Philippines (ICpEP) will have a VHDL, Mixed Signals and Sensors Webinar-Workshop on September 28 to October 2, 2020 from
9:00 AM to 12:00 NN.

The Learning Outcomes of the event are the following:
1. Use knowledge in building combinational circuits to construct basic digital circuit components using Verilog HDL.
2. Synthesize basic digital circuits in building storage elements, decoders, counters and registers using ModelSim
4. Differentiate various types of amplifier, analog, digital and mixed signals
5. Simulate amplifier using LTSpice software

Each participant is required to install ModelSim and LTSpice in their respective laptop.
A separate file on the course requirements and on how to install the software is attached to this letter.

A registration fee of Five Hundred Pesos (PhP 500.00) to cover the event management  services, certificates, honorarium of the speaker, and other related expenses will be
collected. Please deposit your registration fee to Institute of Computer Engineers of  the Philippines, Inc.

BDO Unibank, Inc., Sultan Kudarat-Isulan Branch, 0033-0800-9643

For interested participants, you may reserve your slot by pre-registering at:

http://bit.ly/ICPEPTraining_2020 .  Registration is until September 23, 2020.

For inquiries, kindly contact Engr. Neil P. Magloyuan at 0917-7023506 or you may
email him at npmagloyuan@mcm.edu.ph.

See you All!

VHDL-Webinar-Letter-Of-Invitation

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